1. Field of the Invention
The present invention relates to deep submicron MOS transistors and, more particularly, to a deep submicron MOS transistor with an increased threshold voltage.
2. Description of the Related Art
FIG. 1A shows a plan view that illustrates a prior-art NMOS transistor 100. FIG. 1B shows a cross-sectional diagram taken along line 1Bxe2x80x941B of FIG. 1A. As shown in FIGS. 1A and 1B, transistor 100, which is formed in a p-type substrate 110, includes spaced-apart n+ source and drain regions 112 and 114 that are formed in substrate 110, and a channel region 116 that is located between source and drain regions 112 and 114. Source and drain regions 112 and 114, and channel region 116 define an active region.
In addition, transistor 100 includes a gate oxide layer 120 that is formed over channel region 116, and a gate 122 that is formed on gate oxide layer 120 over channel region 116. Transistor 100 also includes a side wall spacer 124 is formed next to and around gate 122 over lower doped regions of source and drain regions 112 and 114. Further, the active region is isolated from adjacent devices by a field oxide region FOX that is formed in substrate 110.
One problem with transistor 100 is that when transistor 100 is formed in a deep submicron fabrication process, such as a 0.12-micron process, using conventional process steps, transistor 100 can end up having a threshold voltage of about 0.25V with an operating voltage of about 1.2V.
With a threshold voltage this low, it is very difficult to form closely-matched (ideally-matched) MOS transistors, which is a common requirement in analog circuits, because small variations in a 0.12-micron process have a much bigger impact than do the same variations in, for example, a 0.35-micron process.
In addition, when ground is applied to gate 122 of transistor 100 to turn off transistor 100, small noise spikes in the 0.3V range can inadvertently turn on transistor 100. Thus, there is a need for deep submicron MOS transistors that have increased threshold voltages without sacrificing or limiting the current characteristics (e.g., IDSAT) of the transistor.
The present invention provides a deep submicron MOS transistor with a substantially increased threshold voltage. A transistor in accordance with the present invention is formed in a semiconductor material of a first conductivity type, and has spaced-apart source and drain regions of a second conductivity type that are formed in the semiconductor material.
The source region includes a first lightly-doped region, and a first heavily-doped region that is formed in the first lightly-doped region. In addition, the source region includes a second heavily-doped region that adjoins the first lightly-doped region and is spaced apart from the first heavily-doped region.
The drain region includes a second lightly-doped region, and a third heavily-doped region that is formed in the second lightly-doped region. In addition, a fourth heavily-doped region adjoins the second lightly-doped region and is spaced apart from the third heavily-doped region.
The transistor can also include a channel region that is located between the source and drain regions, and a gate oxide layer that is formed over the channel region, the source region, and the drain region. Further, a channel gate is formed on the gate oxide layer over the channel region.
In addition, the transistor can include a side wall spacer that adjoins the side walls of the channel gate, and a side wall gate that adjoins the side wall spacer over the first heavily-doped region. The transistor can further include a gate side wall that adjoins the side wall spacer over the third heavily-doped region. The side wall gate and the gate side wall can be electrically isolated from each other.
The present invention also includes a method of using the MOS transistor. The transistor has ground is applied to the second heavily-doped region, a first positive voltage applied to the fourth heavily-doped region; and a second positive voltage applied to the channel gate. The second positive voltage is equal to or greater than a minimum voltage that is required to invert the channel region of the MOS transistor.
In addition, the transistor is biased off by inducing a first potential substantially equal to ground in the first heavily-doped region, and a second potential substantially equal to ground in the third heavily-doped region. Further, the MOS transistor can be biased from off to on by inducing a third potential equal to or greater than a minimum value on the first heavily-doped region. In addition, a fourth potential equal to or greater than a minimum value is induced on the third heavily-doped region. The fourth potential is greater than the potential required to invert the channel region of the MOS transistor.
The present invention also includes a method of forming a MOS transistor in a semiconductor material of a first conductivity type. The transistor has a layer of gate oxide that is formed over the semiconductor material, and a gate that is formed on the layer of gate oxide over a region of the semiconductor material.
The method includes the step of implanting the semiconductor material with a dopant of the second conductivity type to form a lightly-doped source region and a lightly-doped drain region. In addition, the method includes the steps of forming a side wall spacer that adjoins the side walls of the gate, and forming a side wall gate on the layer of gate oxide to adjoin the side wall spacer over the lightly-doped source region and the lightly-doped drain region.
The method can further include the step of implanting the lightly-doped source region to form to form a heavily-doped source pocket region of the second conductivity type in the lightly-doped source region under the side wall gate. The method can additionally include the step of implanting the lightly-doped drain region to form to form a heavily-doped drain pocket region of the second conductivity type in the lightly-doped drain region under the gate side wall.
Further, the method can include the step of forming a heavily-doped source region of the second conductivity type that adjoins the lightly-doped source region and is spaced away from the source pocket region, and a heavily-doped drain region of the second conductivity type that adjoins the lightly-doped drain region and is spaced away from the drain pocket region.